In a silicon carbide semiconductor device, it has been conventionally demanded to reduce a loss when power is applied (ON-state power loss), and reduce a loss caused during switching of the device (switching loss).
Named as a method to solve this is to reduce a feedback capacitance that depends on a facing area between a drain electrode and a gate electrode. Specifically, as indicated in Patent Document 1, this is a method to reduce an area (JFET region) between a p-base layer and a p-base layer constituting individual unit cells by insertion of p-extraction regions.
According to an n-channel DMOS (Double Diffused MOS) which is a silicon carbide semiconductor device indicated in Patent Document 1, a p-base layer constituting each unit cell is partially connected in the p-extraction region between the unit cells so as to short-circuit the p-base layer to a source electrode through the p-extraction region. With this structure, a noise applied to an element can be also passed to a path leading to the source electrode through the p-extraction region, and a breakdown voltage of the element can be also improved. Further, since the p-region continuously forms one region in the entire element, a local potential increase of the p-base layer is suppressed, and the breakdown voltage of the element can also be improved.